This invention relates to an address translation device for use in combination with a main storage of an information processing system in translating an input virtual address into an output real address.
Such an address translation device is disclosed in U.S. Pat. No. 3,761,881 issued to Anderson et al. In order to make several computer programs, executed either by a single central processing unit or by a plurality of processing units, share one memory, an information processing system is provided with a virtual storage having an extremely large storage capacity which is often more than that of an actual main storage. The virtual storage is divided into virtual pages with each virtual page consisting of a predetermined number of bytes, while the main storage is divided into real pages with each real page consisting of the predetermined number of bytes. The virtual pages are located randomly into the real pages. The virtual pages and the real pages can be exchanged with each other if necessary. Random location of pages necessitates the construction of a page table that reflect the actual or real location of each page. The page table is maintained in the main storage and is utilized in translating an input virtual address into an output real address of the required page.
However, the main storage is frequently referenced whenever address translation of a virtual address into a real address is carried out to read the requested data in the main storage.
In order to solve such a problem, an address translation device comprises an address translation buffer in the central processing unit that may be called a Translation Lookaside Buffer (TLB). More specifically, the address translation buffer memorizes a plurality of virtual addresses and a plurality of real addresses corresponding to the respective virtual addresses. A predetermined part of the input virtual address is supplied to the address translation buffer as a buffer access address. If the address translation buffer contains a particular one of the real addresses that corresponds to the input virtual address, the address translation buffer produces the particular real address as the output real address from the buffer access address. The output real address is used for accessing the main storage. The central processing system may include a buffer storage which may be called a cache storage. In this case, the output real address is sent to the buffer storage.
If the address translation buffer does not contain any one of the real addresses that corresponds to the input virtual address, then the input virtual address is passed on to the main storage and address translation of the input virtual address into the output real address is performed with reference to the page table. Subsequently, the output real address is stored in the address translation buffer together with the input virtual address. Accordingly, the address translation buffer can produce the output real address when the address translation buffer is supplied with the same buffer access address once more again. This is because the address translation buffer already contains the particular real address that corresponds to the input virtual address.
A conventional address translation device comprises a virtual address register, the address translation buffer, and a virtual address comparator. The virtual address register holds, as a held virtual address, the input virtual address supplied from an execution processing unit in the central processing unit. The held virtual address is divided into first and second fields which occupy upper and lower bits thereof, respectively. The second field of the held virtual address is supplied to the address translation buffer as the buffer access address. The address translation buffer stores buffer fields of virtual addresses and real addresses corresponding to the respective virtual addresses. Each of the buffer fields of the virtual addresses corresponds to the first field of the held virtual address. Therefore, responsive to the buffer access address, the address translation buffer produces, as an output buffer field of the virtual address and the output real address, one of the buffer fields of the virtual addresses and one of the buffer real addresses, respectively, that are stored in the buffer access address.
The output buffer field of the virtual address is supplied to the virtual address comparator from the address translation buffer. The virtual address comparator is also supplied with the first field of the held virtual address from the virtual address register. The virtual address comparator compares the first field of the held virtual address with the output buffer field of the virtual address to determine whether or not translation pair corresponding to the input virtual address is stored in the address translation buffer. The virtual address comparator produces a virtual address coincidence signal when the first field of the held virtual address coincides with the output buffer field of the virtual address. When the virtual address comparator produces the virtual address coincidence signal, the address translation buffer produces the output real address which is correctly translated. The main storage is accessed by the output real address.
In general, the address translation buffer is composed by a memory having a large buffer capacity and a relatively longer buffer access time. As a result, the conventional address translation device is defective in that the address translation of the input virtual address into the output virtual address wastes a translation time longer than the buffer access time. That is, the conventional address translation device results in degradation of performance of the information processing system.